1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
Among power semiconductor devices are insulated gate bipolar transistors (IGBTs). IGBTs, for example, may be rated for 400V, 600V, 1200V, 1700V, 3300V, or higher voltages; and for example, are used in power conversion equipment such as converters, inverters, and the like.
Power semiconductor devices have to have low loss and high efficiency while at the same time, low noise (i.e. to have electromagnetic compatibility (EMC)). EMC is dependent on the rate of voltage change over time (dV/dt). For example, during inverter operation, the dV/dt is the most apt to increase at the time of low current of the turn-on diode. Therefore, the dV/dt at the time of turn-ON has to be reduced to a suitable value by increasing gate resistance (Rg) and reducing switching speed. However, when the dV/dt at the time of turn-ON is reduced, turn-ON loss (Eon) of the IGBT increases. Thus, improvement of this Eon-dV/dt tradeoff and improvement of the controllability of the dV/dt at the time of turn-ON by Rg is important.
On the other hand, to reduce IGBT loss, the tradeoff relationship (Von-Eoff tradeoff) between the ON voltage Von and the turn-OFF loss Eoff of the IGBT has to be improved. Improving the injection enhancement (IE) effect is known as an effective method of improving this tradeoff relationship. For example, a structure that enhances the IE effect by increasing the thickness of an oxide film on a trench bottom has been reported (for example, refer to M. Sumitomo, et al., Proceedings of IEEE 24th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 17-20, 2012).
Further, by increasing the capacitance between a gate and a source (gate-source capacitance) Cgs, an effect of suppressing ringing may be expected. However, when Cgs is increased excessively, the gate current for switching increases. Therefore, it is preferable that the Cgs be easily adjustable according to application.
A structure has been reported in which in an IGBT having a trench gate structure, a floating p layer in which no channel occurs is provided between adjacent trenches (for example, refer to N. Tokura, IEEJ Transactions on Industry Applications, Vol. 130, No. 6, pp. 728-733, 2010, and Y. Onozawa, et al., ISPSD '07, pp. 13-16, 2007). A structure has been further reported in which in a trench gate IGBT having a floating p layer, a mesa portion between adjacent trenches and in which a channel occurs is reduced in size, thereby enhancing the IE effect (for example, refer to M. Tanaka and I. Omura, ISPSD '12, pp. 177-180, 2012).
FIG. 9 is a cross-sectional view of an active portion of a conventional trench gate IGBT. The active portion is a portion responsible for current driving. As depicted in FIG. 9, a trench-type MOS (metal-oxide-semiconductor) channel is formed on a front surface side of an n−-type semiconductor substrate 1. A gate oxide film 2 and a gate electrode 3 are provided in a trench 4. A p-type layer 6 in which a channel occurs is provided in a mesa portion 5 between adjacent trenches 4.
An n+-type layer 7 is provided in a surface region of the p-type layer 6. The front surface side of the n−-type semiconductor substrate 1 is covered by an interlayer insulating film 8. An emitter electrode 9 is provided on the interlayer insulating film 8, contacts the p-type layer 6 and the n+-type layer 7 through a contact hole, and is electrically connected to the p-type layer 6 and the n+-type layer 7.
To secure the breakdown voltage, on the front surface side of the n−-type semiconductor substrate 1, at a portion facing the mesa portion 5 across the trench 4, a floating p layer 10 in which no channel occurs is provided. On a rear surface side of the n−-type semiconductor substrate 1, an n+-type field stop layer 11, a p-type collector layer 12, and a collector electrode 13 are provided.
FIG. 10 is a cross-sectional view of the active portion of a conventional trench gate IGBT that enhances the IE effect. As depicted in FIG. 10, compared to the conventional trench gate IGBT depicted in FIG. 9, the trench gate IGBT that enhances the IE effect has, at a lower half of the trench 4, an oxide film 14 that is thicker than the gate oxide film 2 of the upper half of the trench 4. As a result, the current density flowing in a region of the same concentration as that of the drift layer of the mesa portion 5 is enhanced, thereby enhancing the IE effect.
A known dummy gate type structure improves the Eon-dV/dt tradeoff and the controllability of the dV/dt at the time of turn-ON by Rg. In the dummy gate type structure, an emitter trench that becomes a dummy gate is filled with, for example, a poly-silicon in place of a gate electrode and near the dummy gate, an n+ emitter region is provided (for example, refer to Japanese Laid-Open Patent Publication No. 2002-353456).
In the dummy gate type structure, during high voltage such as during the first half of turn-ON, a low resistance path along which hole current flows to the emitter electrode occurs consequent to the storage of holes along the emitter trench. As a result, rises in the potential of the floating portion may be suppressed whereby the Eon-dV/dt tradeoff and the controllability of the dV/dt at the time of turn-ON by Rg may be improved.
Another known structure includes a mixture of a trench gate structure and a planar structure in which a gate insulating film and a gate electrode extend in a horizontal direction. Since the source region and the emitter electrode on the planar structure side are not directly connected, no channel occurs on the planar structure side (for example, refer to Published Japanese-Translation of PCT Application, Publication No. 2013-522924). Consequently, without use of an emitter trench, the Eon-Rg tradeoff and the controllability of the dV/dt at the time of turn-ON by Rg may be improved.
Yet another known structure eliminates the floating p layer by providing in the entire mesa region, dummy trenches that contact each other or are sufficiently close to each other (for example, refer to International Publication No. 2011/111500). Elimination of the floating p layer enables the Eon-Rg tradeoff and the controllability of the dV/dt at the time of turn-ON by Rg to be improved.